Computer memory systems typically comprise a plurality of elemental memory storage components, such as discrete Random Access Memory (RAM) chips, aggregations of RAM chips on Single In-line Memory Modules (SIMMs) or Dual In-line Memory Modules (DIMMs). These elemental memory components are available in a variety of storage capacities and organizations. A memory system of a computer may comprise a fixed or varied number of these components of a single storage capacity or of multiple storage capacities. In addition, the components may be aggregated into larger entities of a memory system. A memory array, for example, may comprise multiple DIMMs of a common storage capacity.
A computer having a memory system described above typically employs an address mapping function to direct data requests issued by a processor to the specific memory component or aggregation containing the requested data. The address mapping function generally "maps" the address location of a data request to a memory storage component which is then activated to satisfy the request. Address mapping functions may vary according to the organizations of the memory storage components with the resulting complexity of a function impacting both the performance and flexibility of the computer. For example, if the addressing mapping function is complex in nature, it can delay activation of a memory storage component which increases memory read latency and, in turn, diminishes system performance. A simple address mapping scheme, on the other hand, may exhibit low memory read latency, but may also limit the number of configurations into which the memory storage components may be organized. This latter scheme may limit a system's ability to configure around a failing memory component, as well as limit the system's upgradability.
Interleaving is a memory organization technique wherein memory address locations are distributed consecutively across multiple memory storage components to create a common memory address space. A fully interleaved memory system distributes addresses consecutively across all memory storage components to create a single memory address space for the entire system. FIG. 1 is a schematic block diagram of a conventional fully interleaved memory system 100 comprising a plurality of memory resources which, in this case, are memory arrays. The number sequences shown among the arrays indicate the distribution of consecutive memory addresses. Note that a total of eight arrays are shown with every eighth address mapped to the same array.
The address mapping function for the fully interleaved memory system of FIG. 1 is quite simple: the three low-order bits of a memory address are a binary encoding of an array number that maps to the address. This type of mapping function is fast and efficient, providing little memory read latency penalty. Such a mapping scheme, however, restricts the configurations into which the memory storage components may be organized. Specifically, a fully interleaved memory organization requires that (i) all memory storage components (i.e. arrays) be of a common storage capacity and (ii) the number of memory storage components (i.e. arrays) be a power-of-2.
Stacking is another memory organization technique wherein the system memory address space is divided into a plurality of memory address sub-spaces. Consecutive memory address locations are initially distributed within a first memory address sub-space until all storage capacity within that sub-space is exhausted. Thereafter, subsequent memory address locations are distributed within a second memory address sub-space. This process repeats until all storage locations within all sub-spaces have been assigned addresses.
FIG. 2 is a schematic block diagram of a conventional memory system 200 comprising a plurality of stacked memory resources or arrays. In contrast to the fully inter-leaved system, the stacked memory system 200 contains a number of memory arrays that is not a power-of-2 and the arrays are apportioned into a number of address sub-spaces that is not a power-of-2. Moreover, the arrays are of varied sizes, with array 0 having a capacity of sixteen storage locations, arrays 1 and 2 having capacities of four storage locations, array 3 having a capacity of four storage locations, array 4 having a capacity of two storage locations and array 5 having a capacity of one storage location. It should be noted that in a stacked configuration addresses may be distributed within an address space in an interleaved manner and address sub-spaces, such as address space 1 in FIG. 2, may be formed by combining and interleaving similarly-sized memory storage components.
The address mapping function for a stacked memory system is generally more complex than the mapping function of a fully interleaved memory. In the former case, the mapping function first determines the address sub-space to which a referenced address maps. This determination is generally made based upon the size of the sub-space and the starting address of the sub-space. Next, the address mapping function determines the interleave mapping within an address sub-space in substantially the same manner as a fully interleaved address mapping function; namely, by means of a binary decode of the low order address bits. The additional determination imposed on a stacked memory address mapping function makes such a scheme expensive in terms of memory read latency and system performance. Yet, the flexibility of the stacked mapping scheme allows a wide variety of combinations of memory storage components, regardless of the size or number of those components.
The present invention is directed to a memory address mapping system that supports a third memory organization technique which exhibits desirable properties of both the fully interleaved and stacked memory configurations. This third technique, referred to as a stacked-hybrid configuration technique, assembles memory storage components into one stacked memory address space which is then fully interleaved. Since the entire memory is interleaved, a simple, performance efficient, fully interleaved address mapping function can be employed. While the fully interleaved aspect of the stacked-hybrid configuration mandates that all memory storage components in a stack have compatible interleave capability, thereby restricting the flexibility of the system somewhat, the configuration still allows different memory storage components in a stack to have different capacities.
FIG. 3 is a block diagram of a stacked-hybrid memory system 300 that includes six memory arrays, arranged in two three-deep stacks 310, 320, which is eight-way fully interleaved. Although the arrays of stack 310 differ in size, they are similarly sized with respect to corresponding arrays of stack 320; that is, Arrays A0 and A1 are the same size, Arrays A2 and A3 are the same size, and Arrays A4 and A5 are the same size. In a stacked-hybrid configuration, interleaving is permissible between the similarly-sized pair of arrays from each stack. Referring to A0 and A1, addresses 0-3 are located in A0, addresses 4-7 are in A1, addresses 8-11 are in A0, addresses 12-15 are in A1, and so on. Essentially, the stacked-hybrid memory system 300 presents a single address space interleaved two ways across the pairs of stacks.
As an illustration of a mapping function, refer to the schematic diagram of a conventional memory reference (physical) address 400 shown in FIG. 4. Five bits are needed to encode an array number that maps a 32-resource (array) address space. Similarly, four bits are needed to encode an array number that maps a 16-resource address space. The low-order bits of a memory reference address generally specify the resource within an address space, whereas the high-order bits of the reference specify the address space. In a fully-interleaved memory system, there is only one address space so the high-order address bits do not have to be examined; only the low-order bits need decoding to determine the location of data within the address space.
In contrast, a stack-hybrid configuration may have many different address spaces, each with its own number of interleaved resources. To support this type of system, mechanisms are provided to indicate (i) the size of the address space referenced and (ii) the number of bits needed to determine the interleaving arrangement within the address space; in both cases, the mechanism is typically a mask. The number of bits needed to define an address space may vary depending upon the size of the address space. Combinatorial logic used for address decoding generally requires application of a mask to a memory address issued by a processor to indicate the number of bits needed to define such an address space. Similarly, the logic utilizes masks to assess the number of bits of a particular address space that are needed to resolve the number of interleaved resources. Address mapping may further require comparison operations between the issued memory reference address and an address stored in a mapping register of the system, along with operations to combine an address-based check with an interleaved-based check to determine the resource storing the requested data.
The present invention is directed to a memory address mapping system that provides flexibility in the use of different sized memory resources while providing the latency advantages of a fully-interleaved memory system.